1. Field of Use
This invention pertains to memory systems and more particularly to circuits for controlling the operation of such systems.
2. Prior Art
It is well known that as systems become more complex due to increases in system functionality, delays related to levels of logic circuits and registers, interconnections and packaging use up greater percentages of a system's cycle time. In an effort to reduce delays, efforts have been made to concentrate the control circuits of systems in fixed locations within such systems by employing programmable logic arrays (PLAs), programmable read only memories PROMs and read only memories ROMs, etc.
Such concentration has been primarily limited to the processing units and peripheral controller units wherein PLAs, PROMs and ROMs are used to perform largely decoding functions. An example of such use of PROMs may be found in U.S. Pat. No. 4,245,263 which is assigned to the same assignee as named herein.
While such arrangements reduce considerably the amount of logic circuits, it has been found that such systems still require additional levels of registers and/or logic circuits for generating desired sequences of timing signals. This becomes especially important in memory systems where rows of memory chips must receive timing signals for predetermined periods of time for proper operation.
The proper generation of timing signals becomes even more complicated when the memory system is not located on the same printed circuit board as the system. Hence, considerable amounts of board space must be allocated to control and timing circuits thereby decreasing the amount of board space for the expansion of memory capacity.
Accordingly, it is a primary object of the present invention to provide a memory system which has a minimal amount of circuit complexity.
It is a further object of the present invention to provide a memory system which includes apparatus for generating the desired sequence of timing signals with minimum delay.
It is a more specific object of the present invention to provide a memory board which can expand the capacity of a host main memory system and be constructed as required with minimum circuit complexity.